1. Field of the Invention
The present invention relates to an integrated logic circuit provided with modules and a hierarchical design method thereof.
2. Description of the Related Art
As an integrated logic circuit has been developed to have higher efficiency and larger scale, there occurs a case where thousands of input and Output-stages are included in the top level of hierarchical design. On the other hand, as the circuit components become smaller in size, logic gates become weaker in driving capability, and several repeater cells (buffer gates) must be inserted on the route for wiring a long path between modules. For this reason, the configuration becomes complicated, the number of timing-adjusting positions becomes larger, and timing-error checking and layout correcting are required so many repeated times, in result of extending the design period of semiconductor logic circuit.